The invention relates to a procedure for the transfer of data between at least two modules, connected to each other by way of a serial data bus, under the control of a clock signal. Each module comprises a receiver unit for the reception of the data sent in each case from the other module and a transmitter unit for the transmission of data to another module. The output of a data value by the transmitter unit of one module to another module at the serial data bus, as well as the import of the data value into the receiver unit of the corresponding other module, is initiated by clock signal slopes. This invention further relates to a serial interface for the realization of the procedure.
Normally the modules are interconnected by a serial data dot-and-dash line. Currently used serial interfaces with 2 mA output buffers for both data and clock signals of the superset master modules and subset slave modules have capacitive loading at the output buffers that restricts the maximum bit rate
FIG. 1 illustrates master module 10 and slave module 12 connected by dot-and-dash line 18. Assume for the purpose further explanation that the master module 10 is to receive a data value from the slave module 12. The path of the clock signal from the master module 10 to the slave module 12 is represented by a broken line 18. The path of the data signal from the slave module 12 to the master module 10 is represented by a dot-and-dash line 18. Master module 10 outputs a clock signal to the serial data bus by clock output buffer 14 and a clock signal output 16. The clock signal is received by slave module 12 by clock signal input 20 and is routed to transmitter unit 22 consisting of a register. The transmitter unit 22 then outputs a data value by data output buffer 24 and data signal output 26 to serial data bus 18. The data value enters receiver unit 30, consisting of a register, by data signal input 28 of master module 10. Thus transfer of the data value to this receiver unit 30 is controlled by the clock signal.
FIG. 2 illustrates the temporal relationship in each case and the resulting limitations with respect to the greatest possible bit rate. FIG. 2 illustrates the data transfer process as above-described in general terms with regard to its exact relation to the clock signal CLK. FIG. 2 shows the clock signal CLK (waveform A) internally generated within the master module 10 at the input of the clock output buffer 14. Waveform B is the clock signal output by clock output buffer 14. Waveform C is the data signal output at the data signal output 26 of the slave module 12.
FIG. 2 illustrates the data transfer process is initiated at leading edge 32, the so-called transmission edge. In this context it should be noted that a high clock signal value is recognized as valid only when it has reached at least 0.7 of the value of the available supply voltage VCC of the CMOS circuits of this example. At time t1 in FIG. 2, the slave module 12 recognizes at its clock signal input 20 and therefore in its transmitter unit 22, the presence of the transmission edge of the clock signal. Slave module 12 causes receiver unit 22 to output a data value to data signal output 26 via buffer 24. As shown in FIG. 2, depending on whether the data value represents a logic 1 or a logic 0, the signal at output 26 begins to increase or to decrease. While the data value at the data signal output 26 reaches the valid value of 0.7 VCC (if the data value is a logic 1) or 0.3 VCC (if the data value is a logic 0) a time period of ΔT3 will elapse. It is only as from time t2 that a valid data value is present at the data signal input 28 at the receiver unit 30 of the master module 10. The transfer of the data value into the receiver unit 30 is initiated by the falling slope 34 of the clock signal, which occurs at the point in time t3, but only becomes effective at the point in time t4 for the above-mentioned reasons. To ensure a correct data transfer, the data value must already be present at the receiver unit 30 at during the pre-determined period time ΔT2 before time t4. This time period ΔT2, referred to as “set-up time”, is necessary to enable the reception units (normally D flip-flops) in the receiver unit 30 to reach a stable condition before the occurrence of the edge of the clock signal that initiates the transfer.
A further time period that has to be considered is the time period ΔT1. Time ΔT1 corresponds to the rising time of the clock signal from 0.3 VCC to 0.7 VCC. This time period ΔT3 must be taken into consideration in case the least favorable condition obtains, when the threshold values for the high voltage are near 0.7 VCC at both the master module and the slave module.
When considering the temporal interrelations described, the greatest possible bit rate can be calculated from the following formula:
      B    ⁢                  ⁢          R      max        =      1          2      ⁢              (                              Δ            ⁢                                                  ⁢            T1                    +                      Δ            ⁢                                                  ⁢            T2                    +                      Δ            ⁢                                                  ⁢            T3                          )            
Using as an example a serial interface as embodied in the integrated circuit TMS470R1x of Texas Instruments Inc., a maximum bit rate of 7.6 Mbits/s can be obtained at both the clock signal output 16 of the master module and at the data output 26 of the slave unit, into a capacitive load of 100 pF, when the parameters ΔT1=37 ns, ΔT2=12 ns and ΔT3=17 ns are assumed.